The present invention relates generally to lock detection circuits and more particularly to a lock indicator circuit which reliably locks over a wide range of frequencies.
Lock detector circuits are well known and utilized extensively to ensure that a circuit is operating at a particular frequency. FIG. 1 is a block diagram of a conventional lock indication circuit 10 that generates a beat frequency that is proportional to a difference in frequencies of two signals. This circuit 10 is the basis of a frequency lock detection system by further processing of the beat signal.
The lock detector circuit 10 includes a beat generator circuit 11. The beat generator circuit 11 comprises a flip flop 12 which receives a reference clock signal at a data input, a recovered clock signal (or clock signal) at a clock input and a reset signal at a clear input. A first output signal is coupled to a delay element 14 which provides an input to a logical operator, in this case, an exclusive OR gate 16. In addition, a second output signal is provided directly to the logical operator 16 from the output of the flip-flop 12. The exclusive OR gate 16 then provides a beat signal which is proportional to the difference in frequencies of the reference clock signal and the recovered clock signal. The beat signal is provided along with the two clock signals to an oscilloscope 22.
FIG. 2 illustrates the reference clock, recovered clock and beat frequency signals produced for the detection circuit 10. As is seen in FIG. 2, the operation of the conventional lock detection circuit 10 is shown for the case where the reference clock frequency equals 1.1 times the recovered clock frequency. As the reference clock gets closer in frequency to the recovered clock, the beat frequency reduces. As the two clocks get further apart, the beat frequency increases. Accordingly, when the reference clock equals the recovered clock, no beat occurs and the signal can be used to indicate an in-lock condition. Typically these circuits do not reliably indicate lock over wide frequency differences between the recovered and reference frequencies. The lock indication typically fails if the reference is at a harmonic or sub-harmonic of the recovered frequency unless an elaborate frequency measurement technique is employed.
To illustrate this problem, refer now to FIG. 3. FIG. 3 illustrates the signals of FIG. 2 when the reference clock frequency is an even number times the recovered clock frequency. As is seen, the circuit 10 fails when the reference clock is exactly P times the recovered clock frequency, where P is an even number times the clock frequency because no beat signal is produced and a lock condition is falsely indicated.
Accordingly, for applications where the recovered and reference clock frequencies are known beforehand to be within tight limits (+/xe2x88x9225%) then the above identified circuit 10 operates reliably as a lock detector. If the clock frequencies are not known beforehand and these limits are exceeded the lock detector circuit 10 can fail for the above-identified reasons.
Accordingly, what is needed is a system and method for providing a lock indicator which is more reliable over a wide range of frequencies than conventional systems. The present invention addresses such a need.
In a first aspect, a lock indicator circuit is disclosed. The lock indicator comprises a first circuit for providing a first beat signal; and a second circuit for providing a second beat signal. A reference clock signal and a recovered clock signal are provided in a reversed manner to the first and second circuits. In a second aspect, a method for providing a lock indication of a circuit is disclosed. The method comprises the steps of providing a first and second beat signals; and utilizing the first and second beat signals to determine if a lock condition has occurred.
A system and method in accordance with the present invention indicates a lock to the desired reference clock and provides an error or out of lock condition if the recovered frequency is at a harmonic or subharmonic of the reference frequency. This ability to avoid a false lock indication requires very little additional circuitry. A further improvement is that the circuit correctly indicates out of lock condition even in the absence of a reference frequency, caused for instance by a broken signal connection.